Numerous examples of content addressable memories (CAMs) exist including U.S. Pat. No. 6,999,331, granted Feb. 14, 2006 to Huang; U.S. Pat. No. 6,389,579, granted May 14, 2002 to Phillips et al.; and U.S patent application Ser. No. 10/609,756, filed Jun. 20, 2003, by Yen et al. They all refer to a bit of memory as taking from 8 to 16 transistors depending if the content addressable memory is binary, as shown in FIG. 1a, or ternary, as shown in FIG. 1b, and while the demand for fast content addressable memory has grown with the need for address translation in digital communications, the size of the memory has limited the product offerings to under a megabit per chip, while DRAM is approaching a gigabit per chip. At the same time, communications has become increasingly serial. The primary communications input to routers and switches is high-speed serial digital streams of data, much of which is self-clocked. Traditionally the address portion of a packet of data is serially read into a chip by a SERDES, and loaded into a register. Thereafter the register's contents are transferred to the data inputs of the CAM, to get the port address for the transfer of subsequent data stream in the packet.
The latency of the switching operation is critical to the smooth operation of switches and routers, but as can be seen, the content addressable memory operation doesn't begin until after the entire address has been captured. This latency also increases as the number of chips to hold the content addressable data grows because the hits between multiple chips must be resolved before the port address can be determined. Therefore, the ability to economically hold greater amounts of content addressable data would also reduce the latency.
Dynamic random access memory (DRAM) structures are the densest volatile digital memory structures in semiconductor technology. Each bit requires only one transistor and a capacitor, as can be seen in FIG. 2a. Unfortunately, these memories are often quite slow. Alternatively there exists static random access memory (SRAM) structures that require 3 to 6 transistors per bit, as can be seen in FIG. 2b, but are much faster, and require less sense circuitry. Traditionally, both of these types of memories are organized with more word lines than bit fines, since all the bits in a word are accessed at the same time.